Isla: integrating full-scale ISA semantics and axiomatic concurrency models (extended version)

Abstract Architecture specifications such as Armv8-A and RISC-V are the ultimate foundation for software verification correctness criteria hardware verification. They should define allowed sequential relaxed-memory concurrency behaviour of programs, but hitherto there has been no integration full-scale instruction-set architecture (ISA) semantics with axiomatic models, either in mathematics or tools. These ISA can be surprisingly large intricate, e.g. 100k $$+$$ + lines Armv8-A. In this paper we present a tool, Isla, computing behaviours concurrent litmus tests respect to definitions, Sail language, arbitrary Cat language. It is based on generic symbolic engine specifications. We equip tool web interface make it widely accessible, illustrate evaluate RISC-V. The execution valuable also other tasks: used automated test generation Arm Morello prototype architecture, extending CHERI capabilities, Iris program-logic reasoning about binary code above By using authoritative semantics, Isla lets one user instructions high confidence. Moreover, because these give detailed validated definitions aspects systems functionality, by hypervisors operating systems, instruction fetch, exceptions, address translation, our provides basis developing these. demonstrate instruction-fetch virtual-memory models examples Simner et al.